Multilevel Inverters New Reduced Device Count Topologies and Midpoint Based Selective Harmonic Elimination Techniques

dc.contributor.guide	Mulla, Mahmadasraf A.
dc.coverage.spatial
dc.creator.researcher	Kamani, Piyushkumar Lavjibhai
dc.date.accessioned	2022-07-21T05:32:09Z
dc.date.available	2022-07-21T05:32:09Z
dc.date.awarded	2019
dc.date.completed	2019
dc.date.registered	2015
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	xxxii, 209
dc.identifier.uri	http://hdl.handle.net/10603/394148
dc.language	English
dc.publisher.institution	Department of Electrical Engineering
dc.publisher.place	Surat
dc.publisher.university	Sardar Vallabhbhai National Institute of Technology Surat
dc.relation
dc.rights	self
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Multilevel Inverters New Reduced Device Count Topologies and Midpoint Based Selective Harmonic Elimination Techniques
dc.title.alternative
dc.type.degree	Ph.D.