Design and implementation of power efficient 5T sram cell using CNTFETs

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dc.contributor.guideG Mamatha
dc.coverage.spatial
dc.creator.researcherG Suneel Kumar
dc.date.accessioned2023-11-03T09:49:40Z
dc.date.available2023-11-03T09:49:40Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered2018
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/523082
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication
dc.publisher.placeAnantapuram
dc.publisher.universityJawaharlal Nehru Technological University, Anantapuram
dc.relationNo of References 90
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleDesign and implementation of power efficient 5T sram cell using CNTFETs
dc.title.alternativeNo
dc.type.degreePh.D.

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