A novel flip flop based error free area efficient and low power pipeline architecture for finite impulse recursive system

dc.contributor.guide	Saravanan, S
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	K, Raja
dc.date.accessioned	2019-03-25T12:46:10Z
dc.date.available	2019-03-25T12:46:10Z
dc.date.awarded	n.d.
dc.date.completed	2017
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	30cm.
dc.format.extent	xxiii, 130p.
dc.identifier.uri	http://hdl.handle.net/10603/234098
dc.language	Others
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	121-129
dc.rights	university
dc.source.university	University
dc.subject.keyword	Circuitsimulation
dc.subject.keyword	Clockgating
dc.subject.keyword	Dilation
dc.subject.keyword	Flip-flop
dc.subject.keyword	Pipeline
dc.title	A novel flip flop based error free area efficient and low power pipeline architecture for finite impulse recursive system
dc.title.alternative
dc.type.degree	Ph.D.