Design and Reliability of Negative Capacitance Multi Gate fets for Next Generation Electronics

dc.contributor.guide	Narendar, Vadthiya
dc.coverage.spatial
dc.creator.researcher	Sresta, Valasa
dc.date.accessioned	2026-01-27T11:46:45Z
dc.date.available	2026-01-27T11:46:45Z
dc.date.awarded	2025
dc.date.completed	2025
dc.date.registered	2023
dc.description.abstract	Attached
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	xx, 166p.
dc.identifier.researcherid	0000-0002-0586-9149
dc.identifier.uri	http://hdl.handle.net/10603/689848
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Warangal
dc.publisher.university	National Institute of Technology Warangal
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	Multi-Gate fets
dc.subject.keyword	Negative Capacitance
dc.subject.keyword	Next Generation Electronics
dc.title	Design and Reliability of Negative Capacitance Multi Gate fets for Next Generation Electronics
dc.title.alternative	Design and Reliability of Negative Capacitance Multi-Gate fets for Next Generation Electronics
dc.type.degree	Ph.D.