FPGA based reconfigurable system to test  System level design by testbench methodology

dc.contributor.guide	Pasalkar, N B
dc.coverage.spatial	Electronics and Telecommunication Engineering
dc.creator.researcher	Wani, Prakash Waman
dc.date.accessioned	2017-01-24T04:56:52Z
dc.date.available	2017-01-24T04:56:52Z
dc.date.awarded	n.d.
dc.date.completed	2007
dc.date.registered	n.d.
dc.description.abstract	Abstract not available newline
dc.description.note	Bibliography given
dc.format.accompanyingmaterial	None
dc.format.dimensions	-
dc.format.extent	xx, 202p.
dc.identifier.uri	http://hdl.handle.net/10603/125959
dc.language	English
dc.publisher.institution	College of Engineering Pune
dc.publisher.place	Pune
dc.publisher.university	Savitribai Phule Pune University
dc.relation	No. of references 63
dc.rights	university
dc.source.university	University
dc.subject.keyword	Digital circuits, Conventional test setup, VLSI chips, Test benches, FAB testing of ASIC
dc.title	FPGA based reconfigurable system to test System level design by testbench methodology
dc.title.alternative	-
dc.type.degree	Ph.D.