Reliable high speed sram design for low power applications

Abstract

The rapid growth in the semiconductor industry has paved the pathway for newlinetremendous advancement in memory applications. Internet of things (IoT), wireless newlinebody sensor nodes and other high-end applications need power-efficient and reliable newlinememories. Static random-access memory (SRAM) which is the heart of the system-on newlinechip (SoC) cache memory occupies a major part of area due to its importance. The newlinedemand for low power, deeply integrated and high-speed memory results in the trade newlineoff between stability and area of the bit cell, which are the two essential aspects of newlinememory. As technology shrinks, the reliability of the memory gets affected because of newlinevoltage scaling. The SRAM memory is susceptible to two main reliability issues such newlineas sensitivity to process variation and operating conditions, and soft error due to newlineradiation in the working environment. newlineIn this work, a dual driven feedback 10T (DDFB10T) bit-cell is proposed newlinewhich employs dual-feedback with shorter feedback time. To improve static noise newlinemargin (SNM), read path is decoupled from the storage node to improve read stability newlineand the column is bit interleaved to achieve write stability. The stability analysis to find newlineout the acceptable DC noise level involves the calculation of write trip voltage (WTV), newlineread current and write current based on N-curve method. The proposed DDFB10T cell newlineworking at the supply voltage of 0.9 V, achieves 1.5 times higher static voltage noise newlinemargin (SVNM) and 0.48 times lesser WTV when compared to 6T SRAM cell. The newlinesensitivity analysis of the proposed cell using Monte Carlo simulation at 45nm newlinetechnology proves that the proposed bit cell is highly immune against process, voltage, newlineand temperature (PVT) variations. The bit cell exhibits lesser SVNM variability when newlineit is normalized to that of 6T SRAM bit cell. Further, the proposed DDFB10T cell is newlinedesigned with the capability to provide a bit interleaved architecture for reducing half newlineselect issue. newline