Design of Energy Efficient Approximate Multiplier Architectures for Multimedia Applications

Abstract

Recent improvements in digital technology have made it possible to newlinestore, send, and analyse huge amounts of data. Using complex computing methods newlineto effectively handle the growing amount of data in real-time apps is now necessary. newlineThese advancements also pose challenges in improving image quality, such as newlineenhancing contrast and pre-processing. Signal processing algorithms, which involve newlinenumerous arithmetic and logical operations, are implemented in real-time newlineapplications using application-specific integrated circuits (ASICs) or digital signal newlineprocessors (DSPs). Multipliers are essential in most signal-processing algorithms, newlineand their design incorporates various optimization techniques in low-power. It has newlinebeen found that the Wallace tree multiplier can use a scalable compressor design. newlineThe proposed scalable compressors are built with cascade-stage XOR-MUX newlinestructures which allows the design to efficiently extend to larger compressors newlinetargeting higher-order multipliers. A split scalable compressor approach is suggested newlinefor scalable compressors to reduce the propagation delay and decrease the carry newlinedelay. The proposed compressors significantly influence the size and power newlinerequirements of the multiplier. For a 6.9% reduction in area, the scalable multipliers newlineexhibit a 9.3% reduction in power and a 16.7% reduction in time delay compared to newlinethe multipliers designed with 4:2 and 15:4 compressors. In contrast, a 5.3% newlinereduction in the area of a split scalable multiplier shows a decrease of 4.6% in power newlineand a 21.1% reduced time delay newline