Investigation on power estimation and power optimization techniques for CMOS VLSI circuits

Abstract

Design of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the extraordinary levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the power dissipation within acceptable limits. The remarkable reduction in transistor size and the subsequent increase in the more number of devices on a single chip, in combination with the budding demand for portable devices, increases the power consumption which lead to major challenge in Very Large Scale Integration (VLSI) circuit design and testing. So we need to minimize power dissipation in circuits which requires accurate estimation of the dissipated power during the design phase. This helps in avoiding complicated and expensive redesign that might be required due to power constraint violations. This thesis proposes techniques to overcome these challenges during design and test. A Power estimation method for Complementary Metal Oxide Semiconductor (CMOS) VLSI circuits using Back Propagation Neural Network (BPNN) is proposed. Motivation of this work is to develop an automated power estimation techniques for CMOS VLSI circuits using statistical tools like BPNN. It overcomes the disadvantages of power estimation by simulating complex circuits using power simulators. Regression analysis and Mean Square Error analysis is performed to measure the deviation of estimated power from that of actual power results obtained through SPICE/Monte Carlo simulations.