Variable Sampling Period based Frequency Locked Loop for Single Phase Grid Synchronization

dc.contributor.guideSelvajyothi, K.
dc.coverage.spatial
dc.creator.researcherArun, K.
dc.date.accessioned2020-03-30T08:24:38Z
dc.date.available2020-03-30T08:24:38Z
dc.date.awarded
dc.date.completed2017
dc.date.registered25-10-2010
dc.description.abstractComposite observer frequency locked loop (CO-FLL) and modulated cascaded delayed signal cancellation frequency locked loop (mCDSC-FLL) are designed for single-phase grid parameter estimation and is applied to real-time applications. Both the composite observer (CO) and modulated cascaded delayed signal cancellation (mCDSC) estimate the in-phase and quadrature components from a harmonic-rich signal. The CO estimator derived from a waveguide oscillator is designed using pole placement technique and the bandwidth of the CO depends on the assigned pole location. Under drift in frequency condition, there is an error in the magnitude and phase of the estimated signal from the CO and mCDSC estimators. In order to estimate the in-phase and quadrature components accurately, a frequency locked loop is integrated with the estimator. The CO has a trigonometric term cos while mCDSC operation has an integer number of delay elements. In drifting frequency condition, a re-computation of the trigonometric term cos is required for accurate estimation in the CO estimator. In the case of mCDSC estimator an adjustment on the number of delays is needed for the frequency adaption which may not always be an integer. In order to avoid the trigonometric computation in the CO estimator and the variation in the number of delays for the mCDSC operator, the sampling period is adaptively adjusted in synchronism with the input signal frequency. In this thesis, a synchronized adaptive sampling period based frequency locked loops are presented.
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/286392
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeChennai
dc.publisher.universityIndian Institute of Information Technology Design and Manufacturing Kancheepuram
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering and Technology,Engineering,Engineering Electrical and Electronic
dc.titleVariable Sampling Period based Frequency Locked Loop for Single Phase Grid Synchronization
dc.title.alternative
dc.type.degreePh.D.

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