Efficient Arithmetic VLSI Architectures for DWPT Computations based on Approximation

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dc.contributor.guideUsha Shree V and Chandrasekhar Reddy P
dc.coverage.spatial
dc.creator.researcherRenuka G
dc.date.accessioned2025-02-03T10:00:17Z
dc.date.available2025-02-03T10:00:17Z
dc.date.awarded2021
dc.date.completed2021
dc.date.registered2012
dc.description.abstractAttached
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent185pp.
dc.identifier.researcherid
dc.identifier.urihttp://hdl.handle.net/10603/619644
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeKukatpally
dc.publisher.universityJawaharlal Nehru Technological University, Hyderabad
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordCompression Techniques
dc.subject.keywordDWPT Computations using Approximation
dc.subject.keywordEfficient Arithmetic VLSI Architectures
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleEfficient Arithmetic VLSI Architectures for DWPT Computations based on Approximation
dc.title.alternative
dc.type.degreePh.D.

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