Certain investigation on fpga based finite impulse response filter using vedic multiplier approach for vibroarthrography signal

Abstract

Over the past few years, Digital Signal Processing (DSP) techniques have been tellingly influencing innovations in several applications like Biomedical Engineering, speech communication, data communication, and the like. The digital filter is the core block of the Digital Signal Processor here. The design and implementation of Digital Filter in Field Programmable Gate Array (FPGA) and other Very Large-Scale Integration (VLSI) designs provides scaling parameters like high speed, high sampling rates, minimum cost and minimum power dissipation comparable to traditional digital signal processing techniques. Finite Impulse Response Filters (FIR) and Infinite Impulse Response Filters (IIR) are basic digital filters that play a significant role in filtering of speech signals, and other Biosignals in the signal processor. In general, the design and construction of digital filters are based on three functional blocks namely, multiplier, adder and the delay units. The performance parameters of FPGA based digital filters are power, area and, delay which depend on multiplier. Hence, the overall efficiency of the digital filters is based on Multiplier operation. The main aim of this research is to focus and demonstrate the effectiveness of the multiplier technique in the FIR filter. The FPGA based Urdhva Tiryagbhyam Vedic technique has been applied for multiplication with four different architectures which are linked with FIR filter for testing the performance of FIR Vedic Multiplier with Vibroarthrography signal. Vibroarthrography signal is a kind of Biosignal and it conveys the information about the vibration of the human knee during flexion and extension. The Vibroarthrography signal is acquired by an accelerometer sensor and is applied to the FIR filter. newline