Investigations on power performance of cmos processors with pulsed latch multi phase multi frequency and reconfigurable clock controllers

Abstract

Reconfigurable clock controller is the upcoming research area as the modern technology advancement demands the necessity for modification in architecture level of CMOS configuration circuits to meet the performance and power crunch. This research work is about runtime variation of clock source with respect to data activity and to estimate the power performance characteristics. The design complexity in clock utilization is reduced by modifying the clock network in architecture level. The clock network is a bottleneck for designers as it is the major source of dynamic power and as the CMOS processor technology advances the device scaling itself leads to leakage power consumption. This work is concentrated on dynamic power as clock network is the major source of dynamic power at subsequent clock nodes. The proposed work focusses on three major run time modifications in clock network, (1) circuit level clock gating model with proposed reconfigurable pulsed latch circuit and the run time variation is analysed for register data, high data activity, lookup table data, (2) A modification in DLL circuit by varying the delay stages, bias voltage with reconfigurable logic picture and quaternary logic for multiphase and multiplication factor in multifrequency clock signal, (3) A Lookup Table based reconfigurable clock controller is analysed with scalable voltage and frequency ranges for variable clock polarity. Each model of clock network is analysed with 32, 64 and 128 bit CLB blocks. A comparative study is performed with existing variable phase and frequency clock gating techniques and with the proposed reconfigurable clock controller techniques newline