Certain investigations on vlsi based approximate computing elements for image processing applications

Abstract

One of the critical design norms for todayand#8223;s embedded and moble system is energy consumption. Many important efforts have already been dedicated to get better energy efficiency at different stages, from software, to architecture, circuit and device levels. Methods that deal energy for excellence of final solution are usually at the algorithmic level and work with parameters such as quantization stages and accuracy of coefficients, but they use exact building blocks. Any application that can withstand bounded and comparatively small errors from their basic components, stands to gain from inexact but low-power building blocks. The multipliers play a significant role in arithmetic operations for DSP applications. Recent developments in processor design also focus on low power multiplier architecture usage in circuits. Most of such architectures and algorithms extensively perform matrix multiplications as their fundamental operation, while a multiplier is typically an inherently energy-hungry component. Multiplication is a heavily used arithmetic operation that figures prominently in signal processing and scientific applications. Multiplication is hardware intensive, and the main criteria of interest are higher speed, lower cost, and less area. Two significant yet often conflicting design criteria are power consumption and speed. Taking into consideration these constraints, the design of low power multiplier is of great interest. Many research efforts related to multiplier design have been introduced inorder to obtain energy efficiency in VLSI circuits. newline