VLSI Systems for Simultaneous in Logic Simulation

dc.contributor.guide	Saravanakumar S.
dc.coverage.spatial
dc.creator.researcher	Karthik S.
dc.date.accessioned	2018-12-26T11:42:49Z
dc.date.available	2018-12-26T11:42:49Z
dc.date.awarded
dc.date.completed
dc.date.registered
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent
dc.identifier.uri	http://hdl.handle.net/10603/224794
dc.language	English
dc.publisher.institution	CSE
dc.publisher.place	Chennai
dc.publisher.university	Vels University
dc.relation
dc.rights	university
dc.source.university	University
dc.title	VLSI Systems for Simultaneous in Logic Simulation
dc.title.alternative
dc.type.degree	Ph.D.