Design and Implementation of Efficiency Enhanced SHA 3 Architecture for Multimodal Biometric Applications

dc.contributor.guideAnaniah Durai, S
dc.coverage.spatial
dc.creator.researcherSravani, M M
dc.date.accessioned2025-03-24T05:53:32Z
dc.date.available2025-03-24T05:53:32Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered2017
dc.description.abstractThe SHA-3 provides better security among the various crypto techniques, especially newlinefor the biometric template protection. This is evident from the security metric newlineand features of SHA-3 demonstrated in various analysis and reported work. The requirement newlinetowards the efficient implementation of SHA-3 architecture, which suits the newlineSoC biometric applications, are low area and high-speed keccak architecture. In this newlinework considering the salient features of such crypto techniques, base architecture of newlineSHA-3 has been proposed with a synchronized padder module that includes compact newlinedynamic RC generator which feeds the RC value to the permutation block. Different newlinearchitectures by adopting fusion and logical optimization techniques are explored. newlineFurthermore, adoption of the proposed SHA-3 to develop a novel HMRF logic generator newlinethat generates a random Bio-Hash key for encryption is done. The critical patient newlinemedical data is encrypted by utilizing this key with the popular AES algorithm. Additionally, newlinea Write/View/Read-only mode have been designed to access/store the details newlineof the health data with the assistance of P and MP multimodal biometrics. newlineImplementation of this proposed base SHA-3 design on V5 and V7 FPGA devices newlineyielded comparatively high efficiency of around 8.69 Mbps/slices and 9.9 Mbps/slices, newlinerespectively. Later, the enhanced fusion based Dual-f architecture with logically optimized newlinedesign, when implemented on V5 and V7, provided better efficiency of 12.85 newlineMpbs/slices and 15.11 Mbps/slices, respectively. Furthermore, implementation of this newlineHMRF logic on the V7 FPGA, yielded low area of 4191 slices, which is found to be newline38% less when compared to the reported designs. Validation of Write/View/Read-only newlinemode that enables to access/store the details of the health data is done on V7. Satisfactory newlineHET (hardware execution time) for Write/View/Read only mode were 8.268, 8.341 newlineand 8.004 ns, with area being 4339,4306 and 1878 slices respectively. Matching analysis newlineof the key retrieval at decision level has also been ve
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extenti-xiv,142
dc.identifier.researcherid
dc.identifier.urihttp://hdl.handle.net/10603/629423
dc.languageEnglish
dc.publisher.institutionSchool of Electronics Engineering-VIT-Chennai
dc.publisher.placeVellore
dc.publisher.universityVellore Institute of Technology, Vellore
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleDesign and Implementation of Efficiency Enhanced SHA 3 Architecture for Multimodal Biometric Applications
dc.title.alternative
dc.type.degreePh.D.

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