Modeling and simulation of self heating effects in sub 14nm cmos devices

dc.contributor.guide	Dixit, Abhisek
dc.coverage.spatial	Electrical Engineering
dc.creator.researcher	Jain, Ishita
dc.date.accessioned	2022-12-30T04:32:07Z
dc.date.available	2022-12-30T04:32:07Z
dc.date.awarded	2019
dc.date.completed	2019
dc.date.registered
dc.description.abstract	Abstract Available
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent
dc.identifier.uri	http://hdl.handle.net/10603/433854
dc.language	English
dc.publisher.institution	Department of Electrical Engineering
dc.publisher.place	Delhi
dc.publisher.university	Indian Institute of Technology Delhi
dc.relation	TH-5868
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Modeling and simulation of self heating effects in sub 14nm cmos devices
dc.title.alternative	Na
dc.type.degree	Ph.D.